Sreenath S
Design Verification Engineer & RTL Design Engineer
I am an Electronics and Communication Engineering graduate with professional training in Advanced VLSI Design and Verification from Maven Silicon. I have hands-on experience in RTL design, SystemVerilog, UVM, Verilog HDL, and industry-standard EDA tools including VCS, QuestaSim, Vivado, and Tessent Scan.
I enjoy solving complex digital design challenges and developing verification environments that improve design quality and reliability. My goal is to contribute to the semiconductor industry by designing efficient digital systems and ensuring functional correctness through robust verification methodologies.
K. Ramakrishnan College of Engineering
CGPA: 7.40HSE Examination
90%SSLC Examination
85%August 2024 – July 2025
Hands-on RTL Design and SystemVerilog UVM Verification Projects.
Designed and integrated a complete Router 1×3 architecture using Verilog HDL with modular FIFO buffers, FSM controller, and synchronizer.
Designed an RTL bridge converting AHB transactions into APB protocol transfers with a comprehensive SystemVerilog UVM verification testbench.
Developed high-performance image filtering datapath utilizing Rounding-Based Approximate (ROBA) Multiplier and Kogge-Stone Parallel Prefix Adder.
Presented an innovative QR-based student ID system enabling smart campus automation.
Instant digital attendance logging.
One-scan access to student profiles.
Tamper-resistant identity verification.
Digitally connected campus workflows.
Received positive appreciation for innovation and scalability.
To pursue a challenging role in VLSI Design and Verification where I can apply my knowledge of RTL Design, Verilog, SystemVerilog, and UVM while contributing to the development of high-performance semiconductor solutions and continuously enhancing my technical expertise.
ssreenath.srgm@gmail.com
+91 8248848023
linkedin.com/in/sreenath-s-09468b263
github.com/Sree004
Drop a message for job opportunities, verification inquiries, or technical collaborations.